Accurately assess circuit performance by
Accurate determination of circuit performance with hardware vintage, and across different manufacturing facilities requires a consistent set of measurement structures on all wafers. This consistency must be maintained when scaling physical layouts from one technology generation to another.
Dr. Manjul Bhushan had a key role in establishing a methodology for evaluating CMOS technology and product performance based on hardware data at IBM. A combination of hardware data and SPICE simulations are used to develop a comprehensive understanding of power performance at several technology nodes. In model-to-hardware correlation, it is prudent to check if the model predictions match known device physics.
"CMOS Test and Evaluation: A Physical Perspective"
From the back cover: This book extends test structure applications described in Microelectronic Test Structures for CMOS Technology (Springer 2011) to digital CMOS product chips. Intended for engineering students and professionals, this book provides a single comprehensive source for evaluating CMOS technology and product test data from a basic knowledge of the physical behavior of the constituent components. Elementary circuits that exhibit key properties of complex CMOS chips are simulated and analyzed, and an integrated view of design, test and characterization is developed. Appropriately designed circuit monitors embedded in the CMOS chip serve to correlate CMOS technology models and circuit design tools to the hardware and also aid in test debug. Impact of silicon process variability, reliability, and power and performance sensitivities to a range of product application conditions are described. Circuit simulations exemplify the methodologies presented, and problems are included at the end of the chapters.
Authors: Manjul Bhushan and Mark B. Ketchen
Springer, published December 2014. Available in hardcover and ebook
1. Ring oscillators for CMOS process tuning and variability control
Bhushan M, Gattiker A, Ketchen MB, Das KK (2006). IEEE Trans Semicon Manuf 19:10-18
2. An integrated CAD methodology for evaluating MOSFET and parasitic extraction models and variability
Das KK, Walker SG, Bhushan M (2007). Proceedings of the IEEE 95:670-687