OctEval: Superconducting Circuit Fabrication

Integrated planarized process for fabrication of superconducting circuits

Contact: mbhushan@octeval.com

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Junction IV plot Junction cross-section

Setting up a robust and repeatable fabrication process in a research or university laboratory environment, often with shared equipment and materials across several projects, is challenging. Appropriate monitors, test structures and a touch of discipline can alleviate these difficulties.

Dr. Manjul Bhushan led the first university based team that successfully demonstrated planarization using chemical mechanical polishing (CMP) for microelectronic fabrication. She combined high quality Nb/AlOx/Nb trilayers with CMP and electron-beam lithography to fabricate low parasitic capacitance, deep submicron Josephson junctions. These processes were subsequently used to fabricate high-speed digital devices and low noise analog detectors. She set up robust Nb/AlOx/Nb triayer processes in several laboratories in research and industrial establishments (Unisys, MIT Lincoln Laboratory, AT&T Bell Labs and SUNY at Stony Brook) in the mid 1980's through the mid 1990's. She continues to advise in this area today as these remain state-of-the-art processes.

Selected Publications:

1. Nb/AlOx/Nb trilayer process for the fabrication of submicron Josephson junctions and low noise SQUIDs
Bhushan M, Macedo EM (1991). Appl Phys Lett 58:1323-1325
2. Fabrication of high quality deep sub-micron Nb/AlOx/Nb Josephson junctions using chemical mechanical polishing
Bao Z, Bhushan M, Hans S, Lukens JE (1995). IEEE Trans Appl Supercond 5:2731-2734
3. Sub-um planarized Nb-AlOx-Nb Josephson junction process for 125 mmm wafers developed in partnership with Si technology
Ketchen MB, Pearson DJ, Kleinsasser AW, Hu C-K, Smyth M, Logan J, Stawiasz K, Baran E, Jaso M, Ross T, Petrillo K, Manny M, Basavaiah S, Brodsky S, Kaplan SB, Gallagher WJ, Bhushan M (1991). Appl Phys Lett 59:2609-2611