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With continued increase in CMOS chip complexity and need for adaptive testing, embedded sensors in CMOS chips have become critical for monitoring variability and reliability.
Dr. Manjul Bhushan has designed and fielded a variety of such structures on high performance microprocessor chips. Such sensors are used to provide a comprehensive understanding of technology performance and circuit design margins, in determining binning strategies, and in defining guardbands in published product specifications.
"CMOS Test and Evaluation: A Physical Perspective"
From the back cover: This book extends test structure applications described in Microelectronic Test Structures for CMOS Technology (Springer 2011) to digital CMOS product chips. Intended for engineering students and professionals, this book provides a single comprehensive source for evaluating CMOS technology and product test data from a basic knowledge of the physical behavior of the constituent components. Elementary circuits that exhibit key properties of complex CMOS chips are simulated and analyzed, and an integrated view of design, test and characterization is developed. Appropriately designed circuit monitors embedded in the CMOS chip serve to correlate CMOS technology models and circuit design tools to the hardware and also aid in test debug. Impact of silicon process variability, reliability, and power and performance sensitivities to a range of product application conditions are described. Circuit simulations exemplify the methodologies presented, and problems are included at the end of the chapters.
Authors: Manjul Bhushan and Mark B. Ketchen
Springer, published December 2014. Available in hardcover and ebook
1. Data analysis techniques for CMOS technology characterization and product impact assessment
Gattiker A, Bhushan M, Ketchen MB (2006). IEEE international test conference ITC'06, L3.3
2. Product representative "at-speed" test structures for CMOS characterization
Ketchen MB, Bhushan M (2006). IBM J Res Dev 50:451-468
3. Ring oscillator based test structure for NBTI analysis
Ketchen MB, Bhushan M, Bolam R (2007). Proceedings of the 2007 IEEE international conference on microelectronic test structures, 2007, pp 43-47