OctEval: Test Structures

Integrated approach to design, test and characterization of test structures for microelectronic technologies

Contact: mbhushan@octeval.com

 Reduce technology development and manufacturing costs by

test structure schematic Electrical test structures are an essential part of fabrication technologies, whether in a small scale research laboratory or a multi-billion dollar silicon foundry. As microelectronic technologies become more complex and expensive, test structures play a critical role in reducing time to maturity and the cost of development and manufacturing.

Dr. Manjul Bhushan has many years of broad, hands-on experience in the area of microelectronic test structures and experimental design. She worked with IBM's 180 nm to 32 nm CMOS technology nodes, as well as in photovoltaics and superconducting technologies earlier in her career. Key elements of scribe-line test structures for CMOS technology are presented in the book entitled

book cover

"Microelectronic Test Structures for CMOS Technology"

A comprehensive guide to serve as a handbook for professional engineers and engineering students engaged in design, test and statistical data analysis for CMOS technology characterization.
  Authors: Manjul Bhushan and Mark B. Ketchen
  Springer, published August 2011. Available in hardcover and ebook

Selected Publications:

1. High speed test structures for in-line process monitoring and model calibration
Ketchen MB, Bhushan M, Pearson DJ (2005). Proceedings of the 2005 IEEE international conference on microelectronic test structures, 2005, pp 33-38. Best paper award
2. Ring oscillator based technique for measuring variability statistics
Bhushan M, Ketchen MB, Polonsky S, Gattiker A (2006). Proceedings of the 2006 IEEE international conference on microelectronic test structures, 2006, pp 87-92. Best paper award
3. CMOS latch metastability characterization at the 65-nm-technology node
Bhushan M, Ketchen MB, Das KK (2008). Proceedings of the 2008 IEEE international conference on microelectronic test structures, 2008, pp 147-151
4. Circuit and technique for characterizing switching delay history effects in silicon-on-insulator logic gates
Ketchen MB, Bhushan M, Anderson CJ (2004). Rev Sci Instrum 75:768-771